The present invention relates to an improvement of an operational amplifier, and more particularly, it relates to an operational amplifier operable with high performance even at a low voltage.
Recently, a supply voltage for LSIs has been more and more decreased in accordance with higher integration of the LSIs. Furthermore, most of the recent LSIs are hybrid ICs including both an analog circuit and a digital circuit. Although the decreased supply voltage is advantageous in a digital circuit for decreasing power consumption and increasing an operational speed, it is not advantageous in an analog circuit because an S/N ratio and a dynamic range can be decreased.
Furthermore, in accordance with recent spread of portable equipment, an analog circuit is required to cope with various supply voltages in a wide range so as to be stably operated even at a different supply voltage. For example, with regard to electric equipment which can be either stationary or portable, such as a compact disc player, an analog circuit included in the equipment has the same configuration both in the stationary and portable equipment. Therefore, in the cases where a supply voltage of, for example, 5 V is used for the stationary equipment and a supply voltage of, for example, 2 V is used for the portable equipment, the analog circuit is required to be stably operated under application of either voltage.
Moreover, when the supply voltage is decreased, there arises another problem that an analog circuit applicable to an ordinary supply voltage cannot be used without changing its configuration.
This conventional problem will now be described with reference to FIG. 14. FIG. 14 is a diagram of a conventional CMOS operational amplifier including a class-AB output circuit. The class-AB output circuit herein means an output circuit which can drive both a PMOS transistor and an NMOS transistor at the output level with a signal. The class-AB output circuit has a large current driving ability, and hence, is used as a typical output circuit in an operational amplifier for driving a resistance.
In FIG. 14, a reference numeral 50 denotes the class-AB output circuit, which includes a series connection of a PMOS transistor 50-1 and an NMOS transistor 50-2. An output terminal 59 is connected with a node in the series connection. A reference numeral 51 denotes a constant current source, which includes a PMOS transistor 51-1. The PMOS transistor 51-1 is connected with a constant current source bias terminal 56 at its gate. A reference numeral 52 denotes a differential current amplifier at the input level, which includes two PMOS transistors 52-1 and 52-2. The differential current amplifier 52 is connected with the constant current source 51, and the PMOS transistors 52-1 and 52-2 are connected with a negative-phase input signal terminal 57 and a positive-phase input signal terminal 58, respectively at their gates. A reference numeral 53 denotes a current mirror circuit, which includes two NMOS transistors 53-1 and 53-2.
Furthermore, a reference numeral 54 denotes a level shifter, which includes a PMOS transistor 54-1 serving as a constant current source and a PMOS transistor 54-2 for level shifting an output of the differential current amplifier 52. A voltage which has been level-shifted by the PMOS transistor 54-2 is output to the gate of the PMOS transistor 50-1 of the class-AB output circuit 50. A reference numeral 55 denotes a phase compensating circuit, which includes a series connection of a resistance element 55-1 and a capacitance element 55-2.
In the configuration of FIG. 14, to a signal having been input to the differential current amplifier 52, the PMOS transistor 54-2 of the level shifter 54 adds a DC level corresponding to a gate-source voltage of the PMOS transistor 54-2, and the resultant signal is supplied to the gate of the PMOS transistor 50-1 of the class-AB output circuit 50. In a normal state where no current is output from the output terminal 59, the state of the differential current amplifier 52 should be completely symmetrical Accordingly, the following equation holds: ##EQU1## wherein Vdd indicates a supply voltage; Vgs50 indicates a gate-source voltage of the PMOS transistor 50-1 of the class-AB output circuit 50; Vgs54 indicates a gate-source voltage of the PMOS transistor 54-2 of the level shifter 54; Vds53-2 indicates a drain-source voltage of the NMOS transistor 53-2 of the current mirror circuit 53; Vds53-1 indicates a drain-source voltage of the NMOS transistor 53-1 of the current mirror circuit 53; and Vgs53-1 indicates a gate-source voltage of the NMOS transistor 53-1 of the current mirror circuit 53.
Assuming that the three MOS transistors 50-1, 54-2 and 53-1 have the same gate-source voltage Vgs and have the same threshold voltage Vth, since the gate-source voltage of each MOS transistor is required to be higher than its threshold voltage Vth, the following equation holds:
Equation 2: EQU Vdd=3 Vgs&gt;3 Vth
Since the threshold voltage Vth is actually approximately 0.7 V and the gate-source voltage Vgs is required to be higher than the threshold voltage Vth by at least 0.2 V, the supply voltage Vdd is required to be at least 2.7 V or higher. Accordingly, when the supply voltage Vdd is set at a voltage lower than 2.7 V, the conventional operational amplifier cannot be normally operated.
Moreover, when a voltage source having a different voltage is used in the conventional operational amplifier, the value of a current flowing in the steady-state can be disadvantageously varied. This problem will be described next.
The values of currents flowing between the drains and the sources of the three MOS transistors 50-1, 54-2 and 53-1 in the steady-state are respectively represented as follows:
Equations 3: EQU Ids50=K50 (Vgs50-Vth).sup.2 EQU Ids53=K53 (Vgs53-Vth).sup.2 EQU Ids54=K54 (Vgs54-Vth).sup.2
wherein Ids50, Ids53 and Ids54 indicate the values of the drain-source currents in the transistors 50-1, 53-1 and 54-2, respectively; and K50, K53 and K54 indicate current efficiencies of these transistors, respectively.
Since the gate-source voltages Vgs50, Vgs53 and Vgs54 are varied substantially in proportion to the supply voltage Vdd, it is understood that the drain-source current IdS50, Ids53 and Ids54 are varied in proportion to a square of the supply voltage Vdd.
The variation of the drain-source current will now be described with reference to FIG. 16. A potential at a node A in the conventional operational amplifier shown in FIG. 14 is a sum of the ground potential, the gate-source voltage Vgs53-2 of the transistor 53-2 and the gate-source voltage 54-2 of the transistor 54-2, and is determined regardless of the supply voltage Vdd. Therefore, as is shown in FIG. 16, the bias voltage (gate-source voltage) Vgs50-1 of the transistor 50-1 can be retained at a large value when the supply voltage Vdd is high, but can be decreased to a small value when the supply voltage Vdd is low. Thus, the bias voltage Vgs50-1 is varied in accordance with the supply voltage Vdd. As a result, when the supply voltage Vdd is different, a current flowing through the transistor 50-1 of the output circuit 50 is largely varied. Accordingly, the value of a current flowing in the conventional CMOS operational amplifier including the class-AB output circuit in the steady-state is largely varied in accordance with the supply voltage Vdd of a used power supply. The largely varied current value is a serious obstacle in decreasing the power consumption.
As the configuration of an operational amplifier free from this problem, for example, Japanese Laid-Open Patent Publication No. 5-95231 describes an operational amplifier comprising, in addition to a constant current source, a differential current amplifier and a current mirror circuit for controlling an NMOS transistor of an output circuit, another constant current source, another differential current amplifier and another current mirror circuit for controlling a PMOS transistor of the output circuit. In this operational amplifier, an output of the added current mirror circuit is supplied to the current control terminal of the PMOS transistor of the output circuit.
However, in the operational amplifier disclosed in the publication, the differential current amplifier for controlling the NMOS transistor of the output circuit includes two PMOS transistors, while the differential current amplifier for controlling the PMOS transistor of the output circuit includes two NMOS transistors. Since the transistors included in the respective differential current amplifiers thus have reverse polarities, one of the differential current amplifiers has an operational range between a supply voltage Vbb and a voltage Vbb-Vt which is lower than the supply voltage Vbb by a threshold voltage Vt of the transistor. Another differential current amplifier has an operational range between a ground voltage and a voltage Vt which is higher than the ground voltage by a threshold voltage of the transistor. In view of these operational ranges of the differential current amplifiers, the operational amplifier is difficult to be actually used because the input dynamic range thereof is too narrow for usage at a low supply voltage. Moreover, it is necessary to connect a diode with the bias terminal of the output buffer circuit in order to stabilize the DC level, which can disadvantageously decrease the DC gain.